1. Field of the Invention
The present invention is directed to integrated circuit design software used in the manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to estimating net delay with crosstalk delay in an integrated circuit design.
2. Description of Related Art
In a previous design flow used in the manufacture of integrated circuits, path delays are calculated using static timing analysis (STA) to find timing critical nets. A timing critical net is a net that belongs to a timing critical path. A path is timing critical, for example, if it has a timing slack that is less than some positive limit, that is, the propagation delay of the path may not meet setup or hold time specifications due to the effect of crosstalk delay. After placement and detailed routing, a crosstalk analysis is performed to determine the effect of crosstalk interference on net delay, referred to as crosstalk delay. A timing closure step is then performed to detect timing violations in the design, and another placement and detailed routing is performed to resolve the timing violations. The crosstalk analysis is typically based on a transistor level simulation and is highly accurate. A disadvantage of this method is that several iterations may be required to resolve all timing violations. The most time consuming step is timing closure after parasitic analysis, that is, including crosstalk analysis.